The present disclosure relates to a circuit board preferably used as a backplane including, for example, a thin film transistor (TFT).
A thin film transistor (hereinafter, referred to as TFT) typically has three electrodes (terminals) called a gate (G) electrode, a source (S) electrode, and a drain (D) electrode. The source and drain electrodes are provided in the same layer, while the gate electrode is provided in a different layer from that layer.
In the case where a large number of TFTs are integrated to achieve a circuit function, a wiring layer provided in the same layer as that of a source or a drain and a wiring layer provided in the same layer as that of a gate need to be electrically connected to each other. Specifically, there is a need of electric connection between wirings in different layers (a need of interlayer wiring connection). For example, a wiring layer in the same layer as that of the gate electrode is connected to a wiring layer leading to the source or drain in a portion outside the TFT. Various interlayer wiring connection techniques have been previously proposed for the circuit including TFTs (see, for example, Japanese Unexamined Patent Application Publication Nos. 2011-14724 and 2008-147614).